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1 features ? serial peripheral interface (spi) compatible ? supports spi modes 0 (0,0) and 3 (1,1) ? datasheet describes 0 operation ? 33 mhz clock rate ? byte mode and 128-byte page mode for program operations ? sector architecture: ? two sectors with 32k bytes each ? 256 pages per sector ? product identi fication mode ? low-voltage operation ? 2.7 (v cc = 2.7 to 3.6v) ? sector write protection ? write protect (wp ) pin and write disable instructions for both hardware and software data protection ? self-timed program cycl e (75 s/byt e typical) ? self-timed sector erase cycl e (1 second/se ctor typical) ? single cycle reprogramming (erase and program) for status register ? high reliability ? endurance: 10,000 write cycles typical ? data retention: 20 years ? 8-lead jedec soic and 8-lead sap packages description the at25f512a provides 524,288 bits of serial reprogrammable flash memory orga- nized as 65,536 words of 8 bits each. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the at25f512a is available in a space-saving 8-lead jedec soic and 8-lead sap packages. the at25f512a is enabled through the chip select pin (cs ) and accessed via a three-wire interface consisting of serial da ta input (si), serial data output (so), and serial clock (sck). all write cycl es are completely self-timed. block write protection for the entire memory array is enabled by programming the sta- tus register. separate write enable and write disable instructions are provided for additional data protection. hardware data prot ection is provided via the write protect (wp) pin to protect against inadvertent write attempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence. table 1. pin configuration pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input rev. 3345g?flash?8/09 512kbit high speed spi serial flash memory 512k (65,536 x 8) at25f512a for new designs use at25f512b 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead soic 1 2 3 4 8 7 6 5 vcc hold sck si cs so wp gnd 8-lead sap bottom view
2 at25f512a 3345g?flash?8/09 figure 1. block diagram absolute maximum ratings* operating temperature ........................................? 40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. storage temperature .........................................? 65 c to +150 c voltage on any pin with respect to ground ........................................ ? 1.0v to +5.0v maximum operating voltage ............................................ 4.2v dc output current........................................................ 5.0 ma 65,536 x 8
3 at25f512a 3345g?flash?8/09 note: 1. this parameter is characterized and is not 100% tested. notes: 1. preliminary ? subject to change 2. v il and v ih max are reference only and are not tested. table 2. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 20 mhz, v cc = +3.6v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (so) 8 pf v out = 0v c in input capacitance (cs , sck, si, wp , hold )6pfv in = 0v table 3. dc characteristics (1) applicable over recommended operating range from: t ai = ? 40 to +85 c, v cc = +2.7 to +3.6v, t ac = 0 to +70 c, v cc = +2.7 to +3.6v (unless otherwise noted) symbol parameter test condition min typ max units v cc supply voltage 2.7 3.6 v i cc1 supply current v cc = 3.6v at 33 mhz, so = open read 10.0 15.0 ma i cc2 supply current v cc = 3.6v at 33 mhz, so = open write 25.0 35.0 ma i sb standby current v cc = 2.7v, cs = v cc ; sck, si, wp , hold = 0v or v cc 2.0 10.0 a i il input leakage v in = 0v or v cc ? 3.0 3.0 a i ol output leakage v in = 0v or v cc , t ai = ? 40 c to 85 c ? 3.0 3.0 a v il (2) input low voltage ? 0.6 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 2.7v v cc 3.6v i ol = 0.15 ma 0.2 v v oh output high voltage i oh = ? 100 a v cc ? 0.2 v
4 at25f512a 3345g?flash?8/09 notes: 1. the programming time for n bytes will be equal to n x t bpc . 2. this parameter is ensured by characterization at 3.0v, 25 c only. 3. one write cycle consists of erasing a sector, followed by programming the same sector. table 4. ac characteristics (preliminary - subject to change) applicable over recommended operating range from t ai = ? 40 to +85 c, v cc = +2.7 to +3.6v c l = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter min typ max units f sck sck clock frequency 0 33 mhz t ri input rise time 20 ns t fi input fall time 20 ns t wh sck high time 9 ns t wl sck low time 9 ns t cs cs high time 25 ns t css cs setup time 25 ns t csh cs hold time 10 ns t su data in setup time 5 ns t h data in hold time 5 ns t hd hold setup time 15 ns t cd hold time 15 ns t v output valid 9ns t ho output hold time 0 ns t lz hold to output low z 200 ns t hz hold to output high z 200 ns t dis output disable time 100 ns t ec erase cycle time per sector 1.1 s t sr status register write cycle time 60 ms t bpc byte program cycle time (1) 75 100 s endurance (2) 10k write cycles (3)
5 at25f512a 3345g?flash?8/09 serial interface description master: the device that generat es the serial clock. slave: because the sck pin is always an input, the at25f512a always operates as a slave. transmitter/receiver: the at25f512a has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code t hat defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the at25f512a, and the serial output pin (so) wi ll remain in a high impedance state until the falling edge of cs is detected again. this will rein itialize the serial communication. chip select: the at25f512a is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the at25f512a. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial comm unication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the at25f512a has a write lockout feature that can be activated by asserting the wp pin. when the lockout feature is ac tivated, locked-out sectors will be read only. the write protect pin will allow normal read/write operations when held high. when the wp is brought low and wpen bit is ?1?, all write operations to the status register are inhibited. wp going low while cs is still low will interrupt a write to the status register. if the internal status register writ e cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit in the status register is ?0?. this will allow th e user to install the at25f512a in a system with the wp pin tied to ground and still be able to write to the sta- tus register. all wp pin functions are enabled when the wpen bit is set to ?1?.
6 at25f512a 3345g?flash?8/09 figure 2. spi serial interface master: microcontroller slave: at25f512a data out (mosi) data in (miso) serial clock (spi ck) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs si so sck cs
7 at25f512a 3345g?flash?8/09 functional description the at25f512a is designed to interface dire ctly with the synchr onous serial peripheral interface (spi) of the 6800 type series of microcontrollers. the at25f512a utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in table 5. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low transition. write is defined as program and/or erase in this specification. the commands program, sector erase, chip erase, and wrsr are write instructions for at25f512a. write enable (wren): the device will power up in the write disable state when v cc is applied. all write instructions must th erefore be preceded by the wren instruction. write disable (wrdi): to protect the device against inadvertent writes, the wrdi instruction disables all writ e commands. the wrdi instruction is independent of the sta- tus of the wp pin. read status register (rdsr): the rdsr instruction prov ides access to the sta- tus register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruction. during internal write cycles, all other commands will be ignored except the rdsr instruction. table 5. instruction set for the at25f512a instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 x011 read data from memory array program 0000 x010 program data into memory array sector erase 0101 x010 erase one sector in memory array chip erase 0110 x010 erase all sectors in memory array rdid 0001 x101 read manufacturer and product id table 6. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpenxxxxbp0wenrdy
8 at25f512a 3345g?flash?8/09 read product id (rdid): the rdid instruction allows the user to read the manufac- turer and product id of the device. the fi rst byte after the instruction will be the manufacturer code (1fh = atmel), followed by the device code, 65h. write status register (wrsr): the wrsr instruction allows the user to select two levels of protection for the at25f512a. the at25f512a is divided into two sectors where all of the memory sectors can be prot ected (locked out) from write. any of the locked-out sectors will therefore be read only. the locked-out sectors and the corre- sponding status register control bits are shown in table 8. the two bits, bp0 and wpen, are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., wren, t wc , rdsr). the wrsr instruction also allows the user to enable or disable the wp pin through the use of the wpen bit. ha rdware write protection is enabled when the wp pin is low and the wpen bit is ?1?. hardware write protection is disabled when either the wp pin is high or the wpen bit is ?0.? when the device is hardware writ e protected, writes to the status register, including the block protect bit and the wpen bit, and the locked-out sec- tors in the memory array are disabled. the wrsr instruction is self-timed to automatically erase and program bp0 and wpen bits. in order to write the status regis- ter, the device must first be write enabled via the wren instruction. then, the instruction and data for the two bits are enter ed. during the internal write cycle, all instructions will be ignored except rdsr in structions. the at25f512a will automatically return to write disable state at the completion of the wrsr cycle. note: when the wpen bit is hardware write pr otected, it cannot be changed back to ?0? as long as the wp pin is held low. table 7. read status register bit definition bit definition bit 0 (rdy ) bit 0 = ?0? (rdy ) indicates the device is re ady. bit 0 = ?1? indicates the write cycle is in progress. bit 1 (wen) bit 1 = ?0? indicates the device is not write enabled. bit 1 = ?1? indicates the device is write enabled. bit 2 (bp0) see table 8. bits 3?6 are ?0?s when device is not in an internal write cycle. bit 7 (wpen) see table 9. bits 0?7 are ?1?s during an internal write cycle. table 8. block write protect bits status register bits at25f512a bp0 array addresses locked out locked-out sector(s) 0none none 1 000000?00ffff all sectors (1?2)
9 at25f512a 3345g?flash?8/09 read (read): reading the at25f512a via the so pin requires the following sequence. after the cs line is pulled low to select a device, the read instruction is transmitted via the si line followed by the three-byte address to be read (see table 10 on page 10). upon completion , any data on the si line will be ignored. the data (d7?d0) at the specified address is then shifted out onto the so li ne. if only one byte is to be read, the cs line should be driven high after the data comes out. the read instruction can be continued since the by te address is automatically incremented and data will con- tinue to be shifted out. when the highest address is reached, the address counter will roll over to the lowest address, allowing the entire memory to be read in one continuous read instruction. program (program): in order to program the at25f512a, two separate instruc- tions must be executed. first, the cs line is pulled low to select the device, the device must be write enabled via the wren instructi on. then, the program instruction can be executed. the program instruction requires the following sequence. after the cs line is pulled low to select the device, the program instructio n is transmitted via the si line followed by the three-byte address and the data (d7?d0) to be programmed (see table 10 on page 10). programming w ill start after the cs pin is brought high. the low-to-high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit (assuming mode 0 operation). during an internal self-timed programming cycle, all commands will be ignor ed except the rdsr instruction. the ready/busy status of the device can be determined by initiating a rdsr instruc- tion. if bit 0 = ?1?, the program cycle is still in progress. if bit 0 = ?0?, the program cycle has ended. only the rdsr instructi on is enabled during the program cycle. a single program instruction programs 1 to 128 consecutive bytes within a page if it is not write protected. the starting byte could be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. if more than 128 bytes of data are provided, the address counter will roll over on the same page and the previous data provided will be replaced. the same byte cannot be re programmed without erasing the whole sector first. the at25f512a will automati cally return to th e write disable state at the completion of the program cycle. note: if the device is not write enabled (wren), the device will ignore the write instruction and will return to the standby state when cs is brought high. a new cs falling edge is required to re-initiate the serial communication. table 9. wpen operation wpen wp wen protectedblocks unpr otectedblocks status register 0 x 0 protected protected protected 0 x 1 protected writeable writeable 1 low 0 protected protected protected 1 low 1 protected writeable protected x high 0 protected protected protected x high 1 protected writeable writeable
10 at25f512a 3345g?flash?8/09 sector erase (sector erase): before a byte can be reprogrammed, the sector containing the byte must be erased. in order to erase the at25f512a, two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then the sector erase instruction can be executed. the sector erase instruction erases every byte in the selected sector if the device is not locked out. sector address is automatically determined if any address within the sector is selected. the sector erase instruction is internally co ntrolled; it will automatically be timed to completion. during this time, all commands will be ignored except rdsr instruction. the at25f512a wi ll automatically return to t he wrdi state at the comple- tion of the sector erase cycle. chip erase (chip erase): as an alternative to the sector erase, the chip erase instruction will erase every byte in both sectors if the device is not locked out. first, the device must be write enabled via the wren in struction. then the chip erase instruction can be executed. the chip erase instruction is internally controlled; it will automatically be timed to completion. the chip erase cycl e time typically is 2 seconds. during the internal erase cycle, all inst ructions will be ignored exce pt rdsr. the at25f512a will automatically return to the wrdi state at the completion of the chip erase cycle. table 10. address key address at25f512a a n a 15 ? a 0 don?t care bits a 23 ? a 16 table 11. sector addresses sector address at25f512a sector 000000 to 007fff sector 1 008000 to 00ffff sector 2
11 at25f512a 3345g?flash?8/09 timing diagrams (for spi mode 0 (0, 0)) figure 3. synchronous data timing figure 4. wren timing figure 5. wrdi timing s o t v si v i valid in h v il t h t su t dis sck cs t csh v ih v il t css t cs v ih v il t wh t wl t ho v oh v ol hi-z hi-z cs sck si so hi-z wren op-code cs s ck si so hi-z wrdi op-code
12 at25f512a 3345g?flash?8/09 figure 6. rdsr timing figure 7. wrsr timing figure 8. read timing cs sck si so 0123456789101112131415 instruction 76543210 msb high impedance data o u t s ck si 0 12 34 5 6 78 9101112131415 instruction 765432 10 data i n so high impedance cs si sck 3-byte address instruction 23 22 21 3 ... 21 0 high impedance 4 5 6 7 3210 01234567891011282930313233343536373839 so cs
13 at25f512a 3345g?flash?8/09 figure 9. program timing figure 10. hold timing figure 11. sector erase timing sck si so cs 3-byte address 1st byte data-in 128th byte data-in high impedance instruction 23 22 21 3 1 0 6 5 4 3 2 1 0 7 2 0123456789101128293031323334 1051 1052 1054 1053 1055 so hold t cd t hd t hz t lz t cd t hd cs sck x = don?t care bit cs sck si so 0 1 2 3 4 5 6 7 89 10 11 28 29 30 31 instruction x 0 1 0 1 0 1 0 23 22 21 ... 3 2 1 0 3-byte address high impedance
14 at25f512a 3345g?flash?8/09 figure 12. chip erase timing figure 13. rdid timing x = don?t care bit cs sck si so high impedance 012 3 45 6 7 x 011 000 1 12 13 14 15 16 17 18 19 1 9 23 cs sck si so 0 1 2 3 4 5 6 7 8 910 11 x 0 00 0 1 1 1 20 21 22 manufacturer code (atmel) high impedance data out 7 65 4 3 21 0 device code
15 at25f512a 3345g?flash?8/09 ordering information ordering code package operation range at25f512an-10sh-2.7 at25f512ay4-10yh-2.7 8s1 8y4 lead-free/halogen-free/nipdau lead finish industrial temperature ( ? 40 to 85 c) package type 8s1 8-lead, 0.150" wide, plastic gull wing small outline pack age (jedec soic) 8y4 8-lead, 6.00 mm x 4.90 mm body, dual footprint, non-leaded, small array package (sap) options ? 2.7 low-voltage (2.7 to 3.6v)
16 at25f512a 3345g?flash?8/09 packaging information 8s1 ? soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0? ? 8? ? top view end view side view e b d a a1 n e 1 c e1 l
17 at25f512a 3345g?flash?8/09 8y4 ? sap 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. 8y4 , 8-lead (6.00 x 4.90 mm body) soic array package (sap) y4 a 8y4 5/24/04 common dimensions (unit of measure = mm) symbol min nom max note a ? ? 0.90 a1 0.00 ? 0.05 d 5.80 6.00 6.20 e 4.70 4.90 5.10 d1 2.85 3.00 3.15 e1 2.85 3.00 3.15 b 0.35 0.40 0.45 e 1.27 typ e1 3.81 ref l 0.50 0.60 0.70 d1 pin 1 id e1 l b e1 e pin 1 index area a e d a1 a
18 at25f512a 3345g?flash?8/09 revision history document no. comments 3345f removed preliminary status? 3345g added ?for new designs use at25f512b? reference on front page
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